Encounter digital implementation system

Combines the power of RTL synthesis, early design exploration, full-chip prototyping and design implementation, in-design DFM, and final signoff analysis in a single environment
Enables design exploration and accurate chip feasibility analysis, including automated floorplan synthesis and ranking
Supports location-based on-chip-variation technologies and the latest methodologies for statistical timing and leakage analysis and optimization
Productivity and faster time to market
Supports hierarchical methodologies, including bottom-up block-based flows, top-down black-box flows, and hybrid flows with partitioning and time budgeting
Provides a new post-assembly closure flow that enables more transparent hierarchical abstraction during top-level assembly and optimization
Performs fast and accurate optimization and analysis in the flat physical implementation flow by leveraging the new single-step advanced engine for SI and timing analysis
Delivers signoff-driven implementation and intuitive, visual features for global timing, power, and clock debug and diagnostics